This disclosure relates to techniques for decoupling or isolating circuits and portions of circuit packages from high frequency noise on power supply lines and other conductors. An embodiment has an interposer element with a through-semiconductor via forming part of a conductor coupling with operational elements, especially elements stacked on the interposer in a 2D or 3D integrated circuit configuration. An inductor is provided within the interposer, using a conductive coil, or two or more magnetically coupled coils (a transformer), formed along plural layers of the interposer with vias running between the layers adjacent to crossing points. In these or other embodiments, two or more series coupled loops are magnetically coupled, forming a transformer. The series inductance is combined with one or more MOS capacitor arrays (MOSCaps) to provide a low impedance ground path at frequencies above operational circuit frequencies.
Voltage supply circuits to circuit loads inherently have serial resistances that cause the voltage applied a circuit load to vary according to the current amplitude conducted to the load from any given reference voltage associated with the power supply to the load. The internal resistance of the power supply and the serial resistance of the conductors coupling the supply voltage to the various circuit loads are subject to Ohm's law, whereby a voltage drop E=IR reduces the supply voltage at a more positive power supply terminal to the load, and also increases the voltage level at the ground or more negative terminal of the load. Typically, plural circuit loads are successively coupled along power supply conductors, such that current coupled through loads that are closer to the power supply load the supply voltage and produce an IR voltage drop that affects the supply voltage level at loads that are farther along the power supply conductor.
Particularly in digital integrated circuits, various loads comprise switched circuits producing high frequency signals. In connection with complementary metal oxide semiconductor (CMOS) devices such as digital latches and memories, for example, a spike of current is conducted when switching states. Some leakage current is conducted when maintaining a logic state, but leakage current is small amplitude and steady in amplitude, whereas high di/dt signals cause greater problems in terms of noise.
A solution for isolating a circuit load from noise on a power supply is to provide the load with a decoupling circuit. For example, a decoupling capacitor is placed across the power supply terminals of a load circuit, or coupled to power supply conductors nearby and leading into the load circuit. The capacitor is normally charged to a nominal voltage. If IR should droop or the negative level should bounce due to noise or with momentary IR loading of the supply line by the circuit or by neighboring circuits, charge conducted from the decoupling capacitor supplies part of the shortfall.
The capacitor can be deemed to form part of a low pass filter that attenuates noise at frequencies above some cross over frequency that can be determined with reference to capacitance and resistance values. The capacitor is coupled in parallel with the load circuit power supply terminals. The load and its parallel decoupling capacitor are coupled to the power supply through the series resistance of the power supply conductors. The capacitor decouples the load from noise on the power line and from the voltage supply droop and ground bounce the other circuits. It is often appropriate to provide a distribution of decoupling capacitors over the area of a circuit, each decoupling local load devices from noise on the power supply conductors, which may involve parallel conductive paths, conductive surfaces such as ground planes, etc. One technique for decoupling loads at points distributed over the area of a circuit could be to provide an array of decoupling capacitors, each capacitor, or perhaps groups of adjacently placed parallel capacitors, serving a point or node in a circuit. The decoupling capacitors are spaced and distributed over the area of the circuit. Alternatively or additionally, decoupling capacitors are provided at points where a power supply conductor is coupled with a particular circuit element to be decoupled.
In one possible arrangement, the decoupling capacitors are MOS capacitors (“MOScaps”), laid out in the superimposed layers in an integrated circuit element. Where the MOScaps are to function as individual capacitors in a distributed array, each is isolated from nearby adjacent capacitors. Alternatively, the MOScaps are coupled in parallel with one another such that their capacitance is summed.
The term MOS in this context is an acronym for a “metal-oxide-semiconductor” and refers to a configuration typical of a field effect transistors (FETs). The metal represents a gate. Actually in modern MOS devices, the gate is typically a conductive material such as polycrystalline silicon rather than a metal. The oxide represents a dielectric layer under the gate. The semiconductor layer below that is typically silicon. A MOScap resembles a field effect transistor structure, i.e., a metal-oxide-semiconductor configuration formed in superimposed layers, except there are no connections for a source or drain. The device represents a capacitor whose terminals are the gate and the semiconductor body, separated from one another by the dielectric layer. Due to charge carrier depletion, the capacitance of a MOScap is influenced by the voltage applied between the gate and the semiconductor body. There is also some current leakage through a MOScap.
In certain integrated circuit configurations that are now known as multidimensional configurations, operative circuit packages are formed by integrated circuit elements that are stacked one atop another (in 3D configurations) or at least an integrated circuit element is supported on an interposer element that in turn is supported on a base or substrate (2.5D configurations). Circuit packages with distinctly different functions can be employed on upper layers, such as digital memories and processors, and also RF and analog devices, mounted adjacent to one another on a passive interposer in which conductors extend laterally and vertically to make necessary connections to and between the circuit packages.
Conductive areas or “pads” on the underside of respective upper circuit and bear against solder balls resting on the upper side of the lower circuit. Typically a smaller number of input/output and power supply terminals are coupled at the underside of a base or substrate by larger and more widely spaced solder balls. At the next upper connections between stacked elements, more numerous solder balls are provided, each ball being smaller and the balls being more closely spaced to accommodate more electrically conductive paths.
Connections running laterally through the passive interposer are provided by metal or conductive semiconductor material (e.g., polycrystalline silicon) deposited in lines such as in channels formed in a given semiconductor layers by deposition and etching, mechanical polishing, optical resist application and patterned removal and the like. Conductors that extend vertically through a substrate or interposer or intermediate integrated circuit are made by through-semiconductor vias (“TSV”s), as zones of conductive material that are aligned in successive adjacent layers and thus form conductors proceeding up through the layers. Electrical connections that are displaced laterally or longitudinally or be made through lines along a given layer, and combinations of lateral, longitudinal and vertical paths are made so as to establish a variety of potentially complex connections. If a new configuration of operative circuits is to be designed, it remains a relatively simple manner to make the necessary connections from the substantially any solder ball or contact pad at the substrate, through the passive interposer, to any contact pad on the respective operative circuits. These connections are made by planning out the longitudinal, lateral and vertical conductors in the interposer. The interposer typically is a passive connection making block of semiconductor material wherein longitudinal/lateral and vertical conductive paths can be defined to make such connections as required.
In connection with a 2.5D or 3D circuit arrangement, separate decoupling capacitors comprising a capacitor or a group of parallel capacitors, may be provided for each point at which a power supply conductor is coupled through a substrate or passive interposer to an operative circuit element. The amount of capacitance that is effective for decoupling (or, in other words, effective for forming a low pass filter with an appropriate cutoff frequency), is chosen to filter or decouple noise at and above a characteristic noise frequency. A large number of MOScap elements may be needed, coupled in parallel, to provide the capacitance necessary to decouple an operative circuit element, or another discrete load on the power supply terminals.
Parallel capacitance coupled with serial resistance forms a low pass filter against noise propagating along the power supply conductors because the capacitor is charged through the serial resistance of the conductors. It is possible to use an inductor rather than a capacitor as the reactive element in a low pass filter, in which case the inductor is the series element and the parallel resistances at the power supply and at the load are parallel elements. It would be possible theoretically to decouple an operative circuit element from noise on a power line conductor using inductors, but the layered arrangement of a semiconductor lends itself to using MOScaps as the reactive elements of a decoupling circuit. MOScaps are useful in passive circuit interposers at least because there are layers available in which MOScaps are readily formed. But it would be advantageous to reduce the disadvantages of MOScaps, particularly the associated current leakage and the use of large circuit areas, while exploiting the presence of layered circuit devices such as passive circuit interposers in 2.5D and 3D integrated circuits.